The present invention relates to a method for designing a power supply circuit and a semiconductor integrated circuit (a semiconductor chip).
Recently, there has been an increasing need for reducing the power consumption of a semiconductor integrated circuit (a semiconductor chip). In order to reduce the power consumption, it is effective to reduce the voltage. An approach to reduce only the voltage of the internal circuit has been employed, rather than to reduce the voltage of the entire semiconductor integrated circuit, in order to maintain the compatibility of the external interface. This requires a plurality of power sources: one for the external interface and another for the internal circuit. However, employing a plurality of power sources increases the cost. In order to reduce the cost, it is effective to employ an on-chip power supply where a power supply circuit (hereinafter, referred to as a DC/DC converter circuit) whose input is the voltage for the external interface and whose output is the voltage for the internal circuit, which is built into a semiconductor integrated circuit. As such a DC/DC converter circuit, a three-terminal regulator, a switching regulator, and the like, are known.
If a DC/DC converter circuit is mounted on a semiconductor chip, a user (a designer) does not need to provide a dedicated line on the board for providing an extra power supply voltage. This, however, has two problems as follows:
1) To produce a high performance DC/DC converter circuit which does not depend on the designing ability of a designer.
When mounting a DC/DC converter circuit on a semiconductor chip, if a designer newly designs a DC/DC converter circuit, the line resistance in the semiconductor integrated circuit is high and it is difficult to increase the power conversion efficiency. Moreover, with a switching regulator, it is not always possible to produce a high performance DC/DC converter circuit in view of the conversion efficiency and noise resulting from a switching regulator which has substantial switching noise due to its configuration, and which may affect the internal circuit of the chip.
When using a macro cell of a DC/DC converter circuit, even when a high performance macro cell is used, if the DC/DC converter circuit is provided in an area other than the area where various I/O cells are provided (i.e., an area where the internal circuit is provided), the distance between the DC/DC converter circuit and the power supply pad increases, thereby increasing the line resistance accordingly. Therefore, the DC/DC converter circuit will have a low conversion efficiency.
In any case, mounting of a high performance DC/DC converter circuit on a chip is highly dependent on the designing ability of a designer. Therefore, it is difficult to ensure production of a DC/DC converter circuit with a high performance, without depending on the designing ability of a designer (e.g. regardless of whether a designer has knowledge on on-chip power supplies).
2) To produce a flexible, high performance DC/DC converter circuit which meets the requirements of the internal structure of a system LSI without placing a burden on a designer.
When mounting a DC/DC converter circuit on a chip, a flexible design which meets the requirements of a plurality of functional blocks forming the system LSI is required. For example, when a plurality of functional blocks (IP) are provided with an optimal power management corresponding to the operational status of each functional block by using a power management circuit PMC (Power Management Circuit), the same number of DC/DC converter circuit need to be mounted on a chip as the number of functional blocks. In this case, where a DC/DC converter circuits is provided with respect to a functional block. As mentioned above, positioning of a DC/DC converter circuit on chip may reduce the conversion efficiency of the DC/DC converter circuit. It is difficult to determine appropriate positions for the DC/DC converter circuits without increasing the number of designing steps.
The present inventors have addressed the above mentioned problems as follows. A DC/DC power supply circuit cell having a DC/DC conversion function is produced as one type of I/O cell, so that a DC/DC power supply circuit cell can be treated in a manner similar to that for the other I/O cells when determining the position on the semiconductor chip where the DC/DC power supply circuit cell is to be provided. An I/O cell as used herein refers to a cell which is provided as an internal circuit of the semiconductor chip for giving/receiving a signal to/from a functional block. In view of the conversion efficiency and noise, it is preferable to produce beforehand a DC/DC power supply circuit cell having a high performance DC/DC conversion function. After determining the position on the semiconductor chip where the DC/DC power supply circuit cells are to be provided in a manner similar to that for the other I/O cells, various I/O cells including the DC/DC power supply circuit cells are arranged on the semiconductor chip by using an automated I/O cell arrangement tool. This solves the aforementioned problems (1) and (2).
An object of the present invention is to provide a high efficiency DC/DC converter circuit.
Another object of the present invention is to provide a method for designing a semiconductor chip which meets the requirements of the internal structure of the semiconductor chip, without unnecessarily giving a burden a designer.
A power supply circuit according to the present invention is formed on a semiconductor chip, the power supply circuit including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip, so that the above-mentioned objects will be achieved.
The output transistor section may have a surge protection function.
The output transistor section may include a mesh type transistor.
The power supply circuit may be arranged along a periphery of the semiconductor chip excluding four corners thereof.
The power supply circuit includes, as the external input/output terminal, an output terminal for outputting the power supply voltage, a power supply terminal for inputting a power supply voltage to the output transistor section, and a ground terminal for inputting a ground voltage to the output transistor section. The power supply terminal and the ground terminal may be arranged in the vicinity of the output terminal.
The power supply circuit include, as the external input/output terminal, a plurality of output terminals for outputting the power supply voltage, a plurality of power supply terminals for inputting a power supply voltage to the output transistor section, and a plurality of ground terminals for inputting a ground voltage to the output transistor section. The plurality of output terminals, the plurality of power supply terminals, and the plurality of ground terminals may be covered with a common metal.
The semiconductor chip may be arranged so that a bonding wire connecting the output transistor section with a package which seals the semiconductor chip is shortest.
The output transistor section and the control circuit may be arranged in an I/O cell arrangement area.
A method for designing a semiconductor chip according to the present invention includes the steps of: determining positions on a semiconductor chip where a plurality of I/O cells are to be arranged, the plurality of I/O cells including at least one first type I/O cell having a power supply voltage conversion function for converting a first power supply voltage into a second power supply voltage and at least one second type I/O cell having a different function from that of the first I/O cell; and arranging the plurality of I/O cells based on the determined positions on the semiconductor chip, so that the abovementioned objects will be achieved.
The at least one second type I/O cell include an input power supply pad cell for inputting a power supply voltage. The second power supply voltage output from the first I/O cell may be smoothed by a smoothing circuit provided outside the semiconductor chip. The power supply voltage generated by the smoothing circuit may be input to the semiconductor chip through the input power supply pad cell.
The input power supply pad cell may be arranged in the vicinity of a functional block to which the power supply voltage generated by the smoothing circuit is provided.
The first I/O cell may have a control terminal for inputting a control signal which indicates one power supply voltage to be generated from among a plurality of power supply voltages.
The first I/O cell may have a control terminal for inputting a control signal which controls whether to perform or stop the power supply voltage conversion function.
The method for designing a semiconductor chip further includes the step of arranging at least one functional block as an internal circuit of the semiconductor chip. The at least one functional block may include a power management circuit, the power management circuit changing a mode of the power supply voltage conversion function of the first I/O cell corresponding to a predetermined functional block according to an operational state of the predetermined functional block.
The first I/O cell may include an output transistor section for converting the first power supply voltage into the second power supply voltage and a control section for controlling the output transistor section.
The output transistor section of the first I/O cell may have a surge protection function.
The output transistor section of the first I/O cell may include a mesh type transistor.